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Espressif Systems /ESP32-S3 /SENSITIVE /DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1

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Interpret as DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 0DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 0DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 0DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 0DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1

Description

adc_dac dma permission configuration register 1.

Fields

DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0

adc_dac’s permission(store,load) in data region0 of SRAM
DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1

adc_dac’s permission(store,load) in data region1 of SRAM
DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2

adc_dac’s permission(store,load) in data region2 of SRAM
DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3

adc_dac’s permission(store,load) in data region3 of SRAM
DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0

adc_dac’s permission(store,load) in dcache data sram block0
DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1

adc_dac’s permission(store,load) in dcache data sram block1

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data